Conventionally, a storage device formed of a memory such as a dynamic random access memory (DRAM) being a volatile memory and a nonvolatile memory is used in an information processing device. In the storage device, data is accessed on the basis of a command issued by a host computer which is the information processing device. A storage device capable of processing the issued command at a high speed is required for improving processing ability of the information processing device.
The nonvolatile memory requires verification to determine whether writing is normally performed after the data is written and rewriting based on a result of the verification. A NAND flash memory, a resistance RAM (ReRAM), a phase-change RAM (PCRAM), a magnetoresistive RAM (MRAM) and the like corresponds to such nonvolatile memory. The number of times of verification and rewriting differ from one memory cell to another. For example, a physical property of a storage element which stores the data in a memory cell differs from one memory cell to another, so that the number of times of verification also differs from one memory cell to another. Also, in the nonvolatile memory, the storage element may be damaged due to deterioration by the writing. Therefore, the number of times of verification increases in the memory cell with higher writing frequency. With this arrangement, writing time for each page being an access unit also changes for each the page. As a result, time required for writing differs among a plurality of write commands issued to the storage device in which such nonvolatile memory is used. Meanwhile, in a case where the writing is not performed normally although the number of times of verification and rewriting reaches a predetermined limit number, the writing in this page is determined to be unsuccessful. In this case, error handling is performed, for example.
On the other hand, there is stand-by time by activation and precharge of the memory cell at the time of writing in a synchronous DRAM (SDRAM) being a type of the DRAM. Therefore, although time required for writing the data in the memory cell is constant in the SDRAM, execution time of the write command including the stand-by time differs from one command to another. In the storage device in which a plurality of SDRAMs is used, a system of speeding up the process of a plurality of issued write commands is proposed. For example, a system provided with a memory controller including a command history buffer which holds the issued commands and an order control unit which changes command issuing order is proposed (for example, refer to Patent Document 1).